create_clock -period 25.000 -name clk -waveform {0.000 12.500} [get_ports clk]


set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tx_filter[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tx_filter[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tx_filter[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tx_filter[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {port_sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {port_sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports dither]
set_property IOSTANDARD LVCMOS33 [get_ports rxf]
set_property IOSTANDARD LVCMOS33 [get_ports txe]
set_property IOSTANDARD LVCMOS33 [get_ports wr]
set_property IOSTANDARD LVCMOS33 [get_ports si_wu]
set_property IOSTANDARD LVCMOS33 [get_ports spi_clk]
set_property IOSTANDARD LVCMOS33 [get_ports lo_spi_data]
set_property IOSTANDARD LVCMOS33 [get_ports source_spi_data]
set_property IOSTANDARD LVCMOS33 [get_ports lo_le]
set_property IOSTANDARD LVCMOS33 [get_ports lo_ce]
set_property IOSTANDARD LVCMOS33 [get_ports source_le]
set_property IOSTANDARD LVCMOS33 [get_ports source_ce]
set_property IOSTANDARD LVCMOS33 [get_ports rd]
set_property IOSTANDARD LVCMOS33 [get_ports lo_rf_enable]
set_property IOSTANDARD LVCMOS33 [get_ports source_rf_enable]
set_property IOSTANDARD LVCMOS33 [get_ports atten_spi_data]
set_property IOSTANDARD LVCMOS33 [get_ports atten_le]
set_property IOSTANDARD LVCMOS33 [get_ports mixer_enable]
set_property IOSTANDARD LVCMOS33 [get_ports amp_pwdn]
set_property IOSTANDARD LVCMOS33 [get_ports lo_ld]
set_property IOSTANDARD LVCMOS33 [get_ports source_ld]
set_property IOSTANDARD LVCMOS33 [get_ports source_muxout]
set_property IOSTANDARD LVCMOS33 [get_ports lo_muxout]
set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property IOSTANDARD LVCMOS33 [get_ports adc_of]
set_property IOSTANDARD LVCMOS33 [get_ports adc_oe]
set_property IOSTANDARD LVCMOS33 [get_ports adc_shdn]
set_property IOSTANDARD LVCMOS33 [get_ports xadc_vp]
set_property IOSTANDARD LVCMOS33 [get_ports xadc_vn]

set_property PACKAGE_PIN N11 [get_ports clk]
set_property PACKAGE_PIN T10 [get_ports {adc_in[0]}]
set_property PACKAGE_PIN T9 [get_ports {adc_in[1]}]
set_property PACKAGE_PIN P9 [get_ports {adc_in[2]}]
set_property PACKAGE_PIN P8 [get_ports {adc_in[3]}]
set_property PACKAGE_PIN R8 [get_ports {adc_in[4]}]
set_property PACKAGE_PIN T8 [get_ports {adc_in[5]}]
set_property PACKAGE_PIN R7 [get_ports {adc_in[6]}]
set_property PACKAGE_PIN T7 [get_ports {adc_in[7]}]
set_property PACKAGE_PIN R6 [get_ports {adc_in[8]}]
set_property PACKAGE_PIN T5 [get_ports {adc_in[9]}]
set_property PACKAGE_PIN R5 [get_ports {adc_in[10]}]
set_property PACKAGE_PIN T4 [get_ports {adc_in[11]}]
set_property PACKAGE_PIN T3 [get_ports {adc_in[12]}]
set_property PACKAGE_PIN R3 [get_ports {adc_in[13]}]
set_property PACKAGE_PIN T2 [get_ports adc_of]
set_property PACKAGE_PIN T12 [get_ports adc_oe]
set_property PACKAGE_PIN T13 [get_ports adc_shdn]

set_property PACKAGE_PIN A13 [get_ports {tx_filter[3]}]
set_property PACKAGE_PIN A14 [get_ports {tx_filter[2]}]
set_property PACKAGE_PIN B16 [get_ports {tx_filter[1]}]
set_property PACKAGE_PIN A15 [get_ports {tx_filter[0]}]

set_property PACKAGE_PIN D16 [get_ports {port_sw[1]}]
set_property PACKAGE_PIN E16 [get_ports {port_sw[0]}]

#set_property PACKAGE_PIN H8 [get_ports {xadc_vp}]
#set_property PACKAGE_PIN J7 [get_ports {xadc_vn}]

set_property PACKAGE_PIN G1 [get_ports {rx_sw[5]}]
set_property PACKAGE_PIN H1 [get_ports {rx_sw[4]}]
set_property PACKAGE_PIN G2 [get_ports {rx_sw[3]}]
set_property PACKAGE_PIN H2 [get_ports {rx_sw[2]}]
set_property PACKAGE_PIN J1 [get_ports {rx_sw[1]}]
set_property PACKAGE_PIN K1 [get_ports {rx_sw[0]}]

set_property PACKAGE_PIN A8 [get_ports {ft2232_data[7]}]
set_property PACKAGE_PIN A9 [get_ports {ft2232_data[6]}]
set_property PACKAGE_PIN A10 [get_ports {ft2232_data[5]}]
set_property PACKAGE_PIN B9 [get_ports {ft2232_data[4]}]
set_property PACKAGE_PIN B10 [get_ports {ft2232_data[3]}]
set_property PACKAGE_PIN B11 [get_ports {ft2232_data[2]}]
set_property PACKAGE_PIN B12 [get_ports {ft2232_data[1]}]
set_property PACKAGE_PIN A12 [get_ports {ft2232_data[0]}]

set_property PACKAGE_PIN A2 [get_ports rxf]
set_property PACKAGE_PIN A3 [get_ports txe]
set_property PACKAGE_PIN A4 [get_ports wr]
set_property PACKAGE_PIN A5 [get_ports si_wu]
set_property PACKAGE_PIN B4 [get_ports rd]

set_property PACKAGE_PIN K16 [get_ports dither]

set_property PACKAGE_PIN K2 [get_ports mixer_enable]
set_property PACKAGE_PIN L3 [get_ports amp_pwdn]

set_property PACKAGE_PIN N14 [get_ports spi_clk]
set_property PACKAGE_PIN M14 [get_ports lo_spi_data]
set_property PACKAGE_PIN K15 [get_ports source_spi_data]
set_property PACKAGE_PIN G14 [get_ports lo_le]
set_property PACKAGE_PIN F14 [get_ports lo_ce]
set_property PACKAGE_PIN F12 [get_ports source_le]
set_property PACKAGE_PIN F13 [get_ports source_ce]
set_property PACKAGE_PIN C16 [get_ports atten_le]
set_property PACKAGE_PIN B15 [get_ports atten_spi_data]
set_property PACKAGE_PIN P16 [get_ports lo_ld]
set_property PACKAGE_PIN R16 [get_ports source_ld]
set_property PACKAGE_PIN H16 [get_ports source_muxout]
set_property PACKAGE_PIN J16 [get_ports lo_muxout]

set_property PACKAGE_PIN T14 [get_ports lo_rf_enable]
set_property PACKAGE_PIN T15 [get_ports source_rf_enable]

set_property PACKAGE_PIN D1 [get_ports led]

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]


set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports {adc_in[*]}]
set_input_delay -clock [get_clocks clk] -max -add_delay 1.400 [get_ports {adc_in[*]}]

set_input_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports {ft2232_data[*]}]
set_input_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports rxf]
set_input_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports txe]

set_input_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports lo_ld]
set_input_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports source_ld]

set_output_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports {ft2232_data[*]}]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports spi_clk]
set_output_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports wr]
set_output_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports rd]

set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports {rx_sw[*]}]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports {port_sw[*]}]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports {tx_filter[*]}]

set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports lo_ce]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports source_ce]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports source_rf_enable]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports lo_rf_enable]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports mixer_enable]

set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports adc_oe]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports adc_shdn]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports amp_pwdn]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports dither]

set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports atten_le]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports lo_le]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports source_le]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports lo_spi_data]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports source_spi_data]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports atten_spi_data]